(a) of FIG. 75 illustrates an arrangement of a conventional flip-flop which is used in a gate driver for a liquid crystal display device, or the like. A conventional flip-flop (FF) 900 illustrated in (a) of FIG. 75 includes five P channel transistors (p100, p101, p102, p103, p104), five N channel transistors (n100, n101, n102, n103, n104), an SB (set-bar) terminal, an R (reset) terminal, a Q (output) terminal, a QB (inversion output) terminal, and an INITB (initial-bar) terminal. Hereinafter, a signal supplied to the SB terminal is referred to as “SB (set-bar) signal”, a signal supplied to the R terminal is referred to as “R (reset) signal”, a signal supplied to the INITB terminal is referred to as “INITB (initial-bar) signal”, a signal outputted from the Q terminal is referred to as “Q (output) signal”, and a signal outputted from the QB terminal is referred to as “QB (inversion output) signal”. Further, an electric potential of a VDD (high potential power source) is referred to as “Vdd”, and an electric potential of a VSS (low potential power source) is referred to as “Vss”.
Here, the FF900 has an arrangement in which (i) a source of the p100 is connected to the VDD (high potential power source), (ii) a drain of the p100, a drain of the n100, a drain of the p102, a drain of the n102, a gate of the p104, a gate of the n104, and the Q terminal are connected to each other, (iii) a source of the n100 and a drain of the n101 are connected to each other, and (iv) a source of the n101 is connected to the VSS (low potential power source). Further, in the FF900, (i) a source of the p101 is connected to the VDD, (ii) a drain of the p101 and a source of the p102 are connected to each other, (iii) a source of the n102 and a drain of the n103 are connected to each other, (iv) a source of the n103 is connected to the VSS, (v) a source of the p104 is connected to the VDD, (vi) a drain of the p104 and a drain of the n104 are connected to each other, and (vii) a source of the n104 is connected to the VSS. Furthermore, in the FF 900, (i) a gate of the p101, a gate of the n100, and the R terminal are connected to each other, (ii) a gate of the p100, a gate of the n101, a gate of the n103, and the SB terminal are connected to each other, (iii) a source of the p103 is connected to the VDD, (iv) a gate of the p103 is connected to the INITB terminal, and (v) a gate of the p102, a gate of the n102, a drain of the p103, and the QB terminal are connected to each other. The FF900 has an arrangement in which (i) the p100 constitutes a set circuit SC, (ii) the n100 constitutes a reset circuit RC, (iii) the n101 constitutes a priority determining circuit PDC, (iv) the p103 constitutes an initialization circuit IC, (v) the p101 and the n103 constitute latch releasing circuits LRC, respectively, and (vi) the p102, the n102, the p104, and the n104 constitute a latch circuit LC.
(b) of FIG. 75 is a timing chart showing an operation of the FF900, and (c) of FIG. 75 is a truth table of the FF900.
In a case where the SB signal is active (=low) and the R signal is inactive (=high) (a time period t1 shown in (b) of FIG. 75), the FF900 operates as described below. When the SB signal is turned to be active (=low), the p100 (set circuit SC) is turned on. This causes the Q terminal to be electrically connected to the VDD (high potential power source) via the p100. The Q signal is therefore turned to be active (=high). The SB terminal is electrically connected to the gate of the n103. Since the n103 (latch releasing circuit LRC) is in an off state during a time period in which the SB signal is low, the Q terminal is not short-circuited with the VSS (low potential power source). Accordingly, it is possible to maintain the Q signal to be active (=high) stably. The Q terminal is connected to the gate of the p104 and the gate of the n104. For this reason, during a time period in which the Q signal is high, the p104 is in the off state and the n104 is in an on state. Accordingly, the QB terminal is connected to the VSS (low potential power source) via the n104 electrically, so that the QB signal is turned to be active (=low). The QB terminal is connected to the gate of the p102 and the gate of the n102. For this reason, during a time period in which the QB signal is low, the p102 is in the on state and the n102 is in the off state. Further, during a time period in which the R signal is low, the p101 (latch releasing circuit LRC) is in the on state. Accordingly, the Q terminal is electrically connected to the VDD (high potential power source) via the p101 and p102. As described above, during the time period t1, the Q signal is active (=high), while the QB signal is active (=low)(see A shown in (c) of FIG. 75).
In a case where the SB signal is inactive (=high) and the R signal is inactive (=low) (a time period t2 shown in (b) of FIG. 75), the FF900 operates as described below. When the R signal is turned to be low and the SB signal is turned to be high, the n103 is turned on. In this case, both the p101 and the n103 (latch releasing circuits LRC) are in the on state, so that the latch circuit is constituted by (i) an inverter constituted by the p102 and the n102 and (ii) another inverter constituted by the p104 and the n104 (the latch circuit LC is turned on). Here, since both the p100 (set circuit SC) which supplies VDD to the Q terminal and the n100 (reset circuit RC) which supplies Vss to the Q terminal are in the off state, no electric potential is supplied to the latch circuit LC. In such a latch state, a state in which the SB signal has not been changed is retained, that is, the state of the time period t1 (the Q signal is high, while the QB signal is low) is retained during the time period t2 (see C shown in (c) of FIG. 75).
In a case where the SB signal is inactive (=high) and the R signal is active (=high) (a time period t3 shown in (b) of FIG. 75), the FF900 operates as described below. When the R signal is turned to be active (=high), the n100 (reset circuit RC) is turned on. Since the SB signal is high, the n101 (priority determining circuit PDC) is in the on state. Since both the n100 and the n101 are in the on state, the Q terminal is connected to the VSS electrically. The p101 (latch determining circuit) is in the off state during a time period in which the R signal is high, so that the Q terminal and the VDD would not be short-circuited with each other. Accordingly, it is possible to maintain the Q signal to be inactive (=low) stably. Further, since the n104 is in the off state and the p104 is in the on state during a time period in which the Q signal is low, the QB terminal is connected to the VDD electrically. As a result, the QB signal is turned to be high. Furthermore, during a time period in which the QB signal is high and the SB signal is high, (i) both the n102 and the n103 (latch releasing circuit LRC) are in the on state and (ii) the p102 is in the off state. Accordingly, the Q terminal is connected to the VSS via the n102 and the n103 electrically. As described above, during the time period t3, the Q signal is inactive (=low) and the QB signal is inactive (=high) (see D shown in (c) of FIG. 75).
In a case where the SB signal is inactive (=high) and the R signal is inactive (=low) (a time period t4 shown in (b) of FIG. 75), the FF900 operates as described below. When the SB signal is turned to be high and the R signal is turned to be low, both the p101 and the n103 (latch releasing circuits LRC) are turned on. This turns on the latch circuit LC. Accordingly, the state in which the R signal has not been changed is retained, that is, the state of the time period t3 (the Q signal is low, while the QB signal is high) is retained during the time period t4.
The initial bar signal (initialization signal), i.e., the INITB signal, is inactive (=high) in a normal state, so that the p103 (initialization circuit IC) is in the off state in the normal state. For initialization of the flip-flop, it is possible to determine an output (Q signal) of the flip-flop forcibly by turning the INITB signal to be active. In the FF900, when the INITIB signal is turned to be active (=low), the p103 is turned on. This causes the QB terminal and the VDD to be electrically connected to each other, so that the QB signal is turned to be high. The n102 is in the on state during a time period in which the QB signal is high. Further, the n103 is in the on state during a time period in which the SB signal is inactive (high). Accordingly, the Q terminal is connected to the VSS via the n102 and the n103 electrically, so that the Q signal is turned to be inactive (=low).
Note that the n101 (priority determining circuit) determines which one of the SB signal and the R signal has priority, in a case where both the SB signal and the R signal are turned to be active simultaneously. In the FF900, in the case where the SB signal is turned to be active (=low) and the R signal is turned to be active (=high), both the p100 and the n100 are turned on. In this case, the n101 (priority determining circuit) is turned off so that the reset circuit RC and the VSS are disconnected from each other electrically, and the Q terminal is connected to the VDD via the p100 electrically. In other words, the SB signal has priority.